Integrated circuit devices currently are being manufactured with a large number of pins, which include input/output pins, pins to be connected to one or more supply voltages (VDD), and pins which are to be connected to ground in the operation of the device. Sixty-four pin integrated circuit devices are common; and large scale integrated circuits, including up to five hundred-twelve pins, currently exist. In the manufacture of integrated circuit devices, and, in many cases, prior to the inclusion of such integrated circuit devices into equipment incorporating these devices, it is desirable to test the operating characteristics of devices. Typically, this is done by a multiple channel tester, which applies the required power supply and ground potentials to selected pins of the integrated circuit device under test (DUT), and also supplies signals to and receives signals from the input/output (I/O) pins of the device under test. The integrated circuit tester equipment typically is interconnected with an integrated circuit device under test (DUT) by means of a load board, which provides the desired interface between the tester and the device to be tested.
Load boards or performance boards for testing integrated circuit devices are relatively complex and expensive. Frequently, load boards are custom designed to provide a specific interface between a particular integrated circuit device which is to be tested and the tester, which is used to operate the device during its test mode of operation.
Typical load boards are printed wire boards, which have a variety of different value chip capacitors soldered to them, depending upon the AC loading specifications of the device to be tested with the particular load board. These chip capacitors are fragile and are unmarked. They can be unknowingly damaged, or the load board fabricator easily can solder an incorrect value capacitor on the load board. The capacitors often are tied to the DUT through relays. The relays may be defective, or they can be knocked off the load board through normal handling. Load board defects of these types easily can go unnoticed, which ultimately results in the shipping of products (DUT's) which have not been tested to the specified capacitive loads.
Typically, load boards are checked, either initially or periodically during their useful lifetime, by test engineers manually measuring the capacitance on a particular pin only if the AC timing measurement on that pin for a DUT is in question. Usually, this manual measurement is only done during the device characterization process, and is rarely re-checked once the board has been released to production. Consequently, if a defect in a capacitor is missed during this initial characterization process check, that defect very well may go unnoticed for the testing of large numbers of DUT's.
Two papers which describe the operation of modern high-speed automatic test equipment for the testing of advanced CMOS devices, dealing with the transmission line effects in testing such devices, are "Transmission Line Testing of CMOS--A Full Implementation" by Gerald C. Cox (paper 20.1--1987 International Test Conference), and "Transmission Line Effects in Testing High-speed Devices with a High-performance Test System" appearing in the Hewlett-Packard Journal, December 1989, pages 58-67. Both of these papers address problems which are encountered by high-speed automatic testers in conjunction with transmission line effects encountered during testing of CMOS integrated circuits. The Cox paper, in particular, deals with the changes to the CMOS rise/fall times, which take place as a result of transmission line effects. This paper also discusses modifications which are made to the test system to achieve matching between the generator and the constant impedance transmission line, which is mismatched at its opposite end.
It is desirable to provide an automated method of verifying the capacitive loads on all DUT signal pins on a load board, which method is easy to implement, and which does not require any external fixtures.